Machine Basics

Data is just data

Without interpretation, data is just garbage. Since machines today adhere to the stored-program concept, any datum could be data or instructions, since instructions are encoded in binary and stored as data in a single storage area. Even if you know a piece of data is data (rather than instructions) you must know what type of data it is to make sense of it. None of this information is part of the data itself.

Memory can be thought of as an array of bytes. Each memory "cell", then, has an address (the index of that datum in the memory "array") and a value. (Note that the simple-machine uses an array of 16-bit values (shorts)). Although real machines use byte-addressable memory, they impose restrictions on how data must be aligned and how it may be accessed, as we will see later.

A very limited amount of special very fast memory is used to hold operands of current operations. The number and restrictions on these registers vary from machine to machine. Typically, data must first be moved into a register before arithmetic or other operations can be performed on it.

The fetch-decode-execute cycle

Program instructions are stored consecutively  in memory corresponding to their sequence in the program. To execute them, the machine operates in a cycle, utilizing two special-purpose registers:

• The Instruction Register (IR) holds the current instruction
• The Program Counter (PC) holds the address of the next instruction

Program execution then proceeds as follows once the program is loaded into memory.

• To begin, the PC is loaded with the address of the first instruction in the program.
• Repeatedly,
• The instruction at memory[PC] is retrieved and placed in the IR (This is called the fetch step.)
• The PC is incremented so that it points to the next instruction. Note that the pc always contains the address of the next instruction to be fetched, not the address of the instruction just fetched.
  
• The instruction is decoded (or taken apart) in the decode step to yield information that indicate the instruction to perform and where the operands are. (How this information is indicated by the instruction is machine-dependent.)
  For example, an arithmetic instruction would indicate

• The operation to perform (the opcode)
• Where the operands are (the operands)
• Where to place the result

• Under what conditions the branch should be taken
• The address of the next instruction to execute if the branch is taken

• Once decoded, the instruction is executed:
• In the case of a branch, instruction execution may alter the PC.
• Certain instruction(s) may cause the program to halt, either due to an error or to normal termination. (This is really just a special case of a branch instruction in a real system.)

Instruction Set Architecture

The set of instructions and capabilities that a machine provides and how they may be used by a programmer form the interface between the machine (hardware) and the lowest level of software. This is called the Instruction Set Architecture. 

There are three common types of ISAs provided by machines:

Stack-based. The best well-known example of a stack-based ISA is the operation of a calculator that works in reverse polish notation (also called postfix notation.) A simple example of postfix would be 3 4 +, which would be written in standard infix notation as 3 + 4. Interestingly, the original MIPS compiler output an intermediary form that is stack-based called UCODE.

Accumulator-based. An accumulator-based ISA has at most a few accumulators that are special-purpose and may be implicit in the instruction. Our Simple Machine is an accumulator-based machine.

General-register. Most computers have general-register ISAs. In this type, information about all operands are encoded in the instruction. Our real machines, MIPS, is a general-register machine, as are all the machines  you would normally know about (ARM, Intel, SPARC, etc.) Register-based machines (accumulator and general register) are also classified traditionally by the complexity of their instructions as CISC (complex instruction set computer) or RISC (reduced instruction set computer), though today RISC is far dominant because they are more regular, easier to generate code for, and far easier to design. (At least, RISC is dominant in numbers of different chips. The only CISC chip remaining in wide use is the Intel chip series, to which has been added RISC instructions.)

Addressing Modes

An operand for an instruction may be in various locations. It may, for example, be in a register. It may also be at a fixed memory address. Alternately, it may be in memory with the address held in a register. In a simpler case, it may be a constant that is encoded in the instruction itself.

The resolution of an operand (i.e., where it is) is specified by its addressing mode. For a given instruction, the addressing mode may be fixed. For example, an add instruction may require that both source operands are in registers, and that the destination is a register. In this case, the instruction simply must indicate which registers are to be used. Alternately, different addressing modes may be available for the same instruction. Another form of the add instruction would have one operand in a register and use a constant as a second operand. The constant must then be specified in the instruction.

One or more operands' locations may also be implicit in the instruction. For example, in the Simple Machine, the MVAC instruction has both operands implicit in the instruction. In MIPS, the mult instruction implicitly places the result of the multiply in a pair of registers named lo and hi, for the low- and high- order result of the multiply operation. Thus, only the source operands are specified in the mult instruction. A following instruction must retrieve the part(s) of the result needed.

As you might expect, the addressing modes available for our Simple Machine are much more limited than those available on our general-purpose machine, MIPS. We will see, however, that they are an interesting subset.

Memory Interface

The simplest view of a memory subsystem is an array of bytes with two associated registers. The first register holds the address of the next memory reference (the MAR or memory address register). The second register is a storage location for a piece of data (the MBR or memory buffer register). A memory "cycle" consists of accessing memory[MAR], either placing the contents of MBR at memory[MAR] (in the case of a memory write) or retrieving the contents of memory[MAR] and placing it in the MBR (a memory read).

A real system is more complicated, of course, as there is a memory transfer size associated. Most systems transfer a set size (say 8 bytes) and extract the appropriate piece of the result as indicated in the instruction.

An instruction cycle includes a memory cycle for the instruction fetch, and [possibly] memory cycle[s] for the instruction execution step. A common restriction of RISC processors is that instruction execution is limited to a single memory cycle. Thus at most one operand of an instruction may be a memory reference.

This simple concept of the memory interface can still be used in the presence of one or more caches. The only difference would be the speed of the memory transfer.

Register Transfer Notation or Language (RTN or RTL)

The complete internal operations of a CPU may be described as a sequence of operations on, and transfers between, registers, and of memory cycles. This notation can be used for descriptive purposes, for simulation (which is done in the case of our Simple Machine's simulator, sim) or for microprogramming in the case of real machines. The RTN (or register transfer language RTL) contains a set of operations, operands which are registers, and a way to specify bitwise pieces of a register. It also allows programming constructs that describe the capabilities of the internal CPU logic. It must, for example, allow a programming construct similar to a switch statement, so that different actions can be taken based on the opcode in the instruction.

The simple RTN we use in the first part of class to describe the Simple Machine is detailed in that machine's description and will not be repeated here.